In arithmetic units or arithmetic-logic units, errors produced by a plurality of causes can occur during routine operation and, when not discovered, can lead to a safety risk, especially when the arithmetic unit is employed in applications that are critical to safety.
A publication by Nicolaidis, "Efficient Implementations of Self-Checking Adders and ALUs", 23rd IEEE International Symposium on Fault Tolerant Computing, Toulouse, France, June 1993, describes where an additional carry look-ahead adder circuit is assigned to an ALU, the duplicated carry bits being checked for identity. By this means, incorrectly generated carry bits and corresponding faulty results from arithmetic logic operations can purportedly be detected. It furthermore provides arithmetic codes for operands, arithmetically combined results for ALUs, and for the checking of these. Reference is made to the following exemplary publications:
[1] Maloff, I. G., Camden, N. J.: Checking Codes for Digital Computers, Proceedings of the IRE, April 1955, pp. 487-488; PA1 [2] Peterson, W. W.: On Checking and Adder, IBM Journal, April 1958, pp. 166-168; PA1 [3] Brown, D. T.: Error Detecting and Correcting Binary Codes for Arithmetic Operations, IRE Transactions on Electronic Computers, September 1960, pp. 333-337; PA1 [4] Lo, J. Ch., Thanawastien, S., Rao, T. R. N., Nicolaidis, M.: An SFS Berger Check Prediction ALU and its Application to Self-Checking Processor Designs, IEEE Transactions on Computer-Aided Design, Vol. 11, No. 4, April 1992, pp. 525-540; PA1 [5] Holzapfel, H. P.: Fehlertolerante VLSI-Prozessoren [Fault-tolerant VLSI Processors], Diss. TU Munich, 1987; PA1 [6] Khodadad-Mostashiry, B.: Parity Prediction in Combinational Circuits, Proceedings of the FTCS-9, IEEE Computer Society, 1979; PA1 [7] Fujiwara, E., Haruta, K.: Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes, The Transactions of the IECE of Japan, Vol. E 64, No. 10, October 1981, pp. 653-660.
A solution entailing parity-bit prediction is introduced in [6] and is expanded upon in [7] to include using error-correcting codes. Common to all the known testing or monitoring devices is that in each case only single, specially occurring faults are able to be detected. Other, faults, however, are not detectable.